This invention generally relates to methods for forming copper filled semiconductor features and more particularly to a method for forming a metal nitride layer over copper filled semiconductor features to suppress the formation of copper hillocks.
Copper metallization is increasingly being used for advanced product integrated circuit fabrication including semiconductor features from sub-micron high aspect ratio interconnect features to larger features such as bonding pads. Copper and its alloys have lower resistivity and better electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving higher current densities with increased device speed. While several processing difficulties related to forming copper semiconductor features have been overcome, several problems remain, especially in backend-of-line (BEOL) manufacturing processes. BEOL processes have traditionally addressed the problems of surface contaminants that adversely affect adhesion of overlying layers, contact formation, and chemical mechanical polishing (CMP).
One exemplary process for forming a multiple level semiconductor device includes, for example, a dual damascene process. Although there are several different manufacturing methods for manufacturing dual damascene structures, all such methods employ at least two photolithographic masking and anisotropic etching steps, for example, first forming vias to electrically interconnect different device levels followed by the formation of an overlying trench at least partially encompassing one or more vias to provide electrical interconnection between multiple device levels and within a device level. In most devices, pluralities of vias are separated from one another along the semiconductor wafer and selectively interconnect conductive regions between levels of a multi-level device. Metal interconnect lines, also referred to as trench lines typically serve to selectively interconnect conductive regions within a level of a multi-level device. Dual damascene formation is a process whereby via openings and trench line openings are formed in one or more dielectric insulating layers to form a dual damascene structure followed by a metal deposition process to fill the dual damascene structure to form the necessary electrical connections.
In forming a copper semiconductor feature, typically a relatively pure (undoped) copper material is deposited to fill an anisotropically etched opening, for example a dual damascene structure. Copper electro-chemical plating (ECP) is a preferable method for depositing copper to achieve superior step coverage of sub-micron etched features. ECP generally includes depositing a copper seed layer over the barrier layer and then electroplating bulk copper over the seed layer to fill the etched feature to form, for example, vias and trench lines. The deposited copper layer is then planarized to remove excess copper overlying the feature level by chemical mechanical polishing (CMP).
One problem affecting BEOL processes in copper metallization is the tendency of copper to easily form oxides of copper, for example CuO or CuO2 upon exposure to oxidizing environments including humid environments. Prior to forming a next level of the device, a metal nitride layer which functions as an etching stop layer in formation of metal interconnect features such as vias or dual damascenes in overlying dielectric insulating layers, is typically deposited over the exposed copper. The overlying etching stop layer also protects the copper against further oxidation.
One problem with prior art processes of forming metal nitride layers over exposed copper is the thermal stresses the copper is exposed to during the process. For example, prior art processes have typically included plasma processes to treat the exposed copper surface followed by metal nitride layer deposition. The prior art plasma processes typically include thermal cycles that result in thermal mismatch stresses building up in the copper layer which results in the formation of hillocks, or sharp copper protrusions into the overlying metal nitride layer. The formation of copper hillocks can result in the shorting of metal interconnects between successively formed layers, including, for example stacked dual damascene structures.
These and other shortcomings in copper feature manufacturing processes demonstrate a need in the semiconductor processing art to develop a method for forming multiple layer devices including copper filled features where copper oxidation is effectively removed prior to formation of overlying layers without subjecting the copper filled features to thermal stresses leading to copper hillock formation.
It is therefore an object of the invention to provide a method for forming multiple layer devices including copper filled features where copper oxidation is effectively removed prior to formation of overlying layers without subjecting the copper filled features to thermal stresses leading to copper hillock formation while overcoming other shortcomings of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method of depositing a plasma enhanced CVD metal nitride layer over an exposed copper surface in a semiconductor wafer manufacturing process to improve the metal nitride layer adhesion and to reduce copper hillock formation.
In a first embodiment the method includes providing a process surface comprising an exposed copper surface; pre-heating the process surface; plasma sputtering the exposed copper surface in-situ to remove copper oxides; and, depositing a metal nitride layer in-situ according to a plasma enhanced CVD process at a selected deposition pressure to reduce plasma ion bombardment energy transfer and to suppress copper hillock formation.